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1 fn8177.7 caution: these devices are sensitive to electrostatic discharge ; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil ame ricas inc. xdcp is a trademark of intersil americas inc. copyright intersi l americas llc 2005, 2006, 2008, 2015. all rights reserved all other trademarks mentioned are the property of their respec tive owners. x9313 digitally controlled potentiometer (xdcp?) linear, 32 taps, 3 wire interface, terminal voltages v cc the intersil x9313 is a digit ally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controll ed by a 3-wire interface. the potentiometer is impleme nted by a resistor array composed of 31 resistive ele ments and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is co ntrolled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including: ? control ? parameter adjustments ? signal processing features ? solid-state potentiometer ? 3-wire serial interface ? 32 wiper tap points - wiper position stored i n nonvolatile memory and recalled on power-up ? 31 resistive elements - temperature compensated - end-to-end resistance range 20% - terminal voltages, -v cc to +v cc ? low power cmos -v cc = 3v or 5v - active current, 3ma max. - standby current, 500a max. ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ?r total values = 1k ? , 10k ? , 50k ? ? packages - 8 ld soic, 8 ld ms op and 8 ld pdip ? pb-free available (rohs compliant) block diagram 5-bit nonvolatile memory store and recall control circuitry one of outputs resistor array r h /v h u/d inc cs transfer gates thirty-two v cc v ss r l /v l r w /v w control up/down v cc (supply voltage) v ss (ground) r h /v h r w /v w r l /v l general detailed 0 1 2 28 29 30 31 (u/d ) increment (inc ) device select (cs ) and memory 5-bit up/down counter time decoder active at a
2 fn8177.7 october 7, 2015 submit document feedback pin descriptions rh/vh and rl/vl the high (rh/vh) and low (rl /vl) terminals of the x9313 are equivalent to the fixed terminals of a mechanical potentiometer. the terminology of rl/vl and rh/vh references the relative position of the terminal in relation to wiper movement directi on selected by the u/d input and not the voltage potential on the terminal. rw/vw rw/vw is the wiper terminal and is equivalent to the movable terminal of a mech anical potentiometer. the position of the wiper within the array is determined by the control inputs. the wiper termi nal series resistance is typically 40 ? at v cc = 5v. up/down (u/d ) the u/d input controls the directi on of the wiper movement and whether the counter is i ncremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either inc rement or decrement the counter in the direction indica ted by the logi c level on the u/d input. ordering information part number part marking v cc range (v) r total (k ? ) temperature range (c) package pkg. dwg. # x9313umiz* (note) ddb 4.5 to 5.5 50 -40 to +85 8 ld msop (pb-free) m8 .118 x9313usz* (note) x9313u z 0 to +70 8 ld soic (pb-free) m8.15 x9313usiz* (note) x9313u zi -40 to +85 8 ld soic (pb-free) m8.15 x9313wmz* (note) ddf 10 0 to +70 8 ld msop (pb-free) m8.118 x9313wmiz* (note) dde -40 to +85 8 ld msop (pb-free) m8.118 x9313wpiz x9313wp zi -40 to +85 8 ld pdip*** (pb-free) mdp0031 x9313wsz* (note) x9313w z 0 to +70 8 ld soic (pb-free) m8.15 X9313WSIZ* (note) x9313ws zi -40 to +85 8 ld soic (pb-free) m8.15 x9313zmz* (note) ddj 1 0 to +70 8 ld msop (pb-free) m8.118 x9313zmiz* (note) ddh -40 to +85 8 ld msop (pb-free) m8.118 x9313zsz* (note) x9313 z 0 to +70 8 ld soic (pb-free) m8.15 x9313zsiz* (note) x9313zs zi -40 to +85 8 ld soic (pb-free) m8.15 x9313umz* (note) ddc 3 to 5.5 50 0 to +70 8 ld msop m8.118 x9313umz-3* (note) ddd 3 to 5.5 50 0 to +70 8 ld msop m8.118 x9313umiz-3* (note) 13uez -40 to +85 8 ld msop (pb-free) m8.118 x9313usz-3* (note) x9313u zd 0 to +70 8 ld soic (pb-free) m8.15 x9313wmz-3* (note) ddg 10 0 to +70 8 ld msop (pb-free) m8.118 x9313wmiz-3* (note) 13wez -40 to +85 8 ld msop (pb-free) m8.118 x9313wsz-3* (note) x9313w zd 0 to +70 8 ld soic (pb-free) m8.15 x9313zmz-3* (note) ddk 1 0 to +70 8 ld msop (pb-free) m8.118 x9313zmiz-3* (note) 13zez -40 to +85 8 ld msop (pb-free) m8.118 x9313zsz-3* (note) x9313z zd 0 to +70 8 ld soic (pb-free) m8.15 x9313zsiz-3* (note) x9313z ze -40 to +85 8 ld soic (pb-free) m8.15 note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020. *add t1 suffix for tape and reel . please refer to tb347 for d etails on reel specifications. **add "t2" suffix for tape and reel. please refer to tb347 for details on reel specifications. ***pb-free pdips can be used for through hole wave solder proce ssing only. they are not intended for use in reflow solder proc essing applications. x9313
3 fn8177.7 october 7, 2015 submit document feedback chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is complete, t he x9313 will be placed in the low power standby mode until the device is selected once again. principles of operation there are three sections of the x9313: the input control, counter and decode section; t he nonvolatile memory; and the resistor array. the input control section operates just lik e an up/down counter. the output o f this counter is decoded to turn on a single electronic swit ch connecting a point on the resistor array to the wiper output. under the proper conditions, the contents of t he counter can be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 31 indivi dual resistors connected in series. at either end of the arra y and between each resistor is an electronic swit ch that transfers t he potential at that point to the wiper. the wiper, when at either fixe d terminal, act s like its mechanical equivalent and does not move bey ond the last position. that is, the counte r does not wrap around when clocked to either extreme. the electronic switches on the device operat e in a make before break mode when the wiper changes tap positions. if the wiper is moved several pos itions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved seve ral positions. when the device is powered-dow n, the last wiper position stored will be maintained in t he nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resis tor array. with cs set low the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a seven bit counter. the output of thi s counter is dec oded to select one of thirty-two wiper positions along the resistive array. the value of the counter is s tored in nonvolatile memory whenever cs transitions high while the inc input is also high. the system may sele ct the x9313, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory . after the wiper movement is performed as previously d escribed and once the new position is reached, t he system must keep inc low while taking cs high. the new wiper pos ition will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored data. this procedure allows the syst em to always po wer-up to a preset value stored in nonvo latile memory; then during system operation, minor adjus tments could be made. the adjustments might be based on user pre ference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. pinouts x9313 (8 ld pdip, 8 ld soic) top view x9313 (8 ld msop) top view table 1. pin names symbol description rh/vh high terminal rw/vw wiper terminal rl/vl low terminal vss ground vcc supply voltage u/d up/down control input inc increment control input cs chip select control input vcc cs inc u/d rh/vh vss 1 2 3 4 8 7 6 5 x9313 rl/vl rw/vw vcc cs u/d rh/vh 1 2 3 4 8 7 6 5 x9313 rl/vl rw/vw inc vss table 2. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current x9313
4 fn8177.7 october 7, 2015 submit document feedback symbol table l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) table 2. mode selection cs inc u/d mode waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance x9313
5 fn8177.7 october 7, 2015 submit document feedback absolute maximum ratings reco mmended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on cs , inc , u/d , and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage on v h , v l , v w with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +7v ? v = |v h - v l |: x9313z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4v x9313w, x9313u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200v temperature: commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (vcc): x9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% x9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 5.5v max wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4ma power rating: r total ? 10k ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mw r total 1k ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mw pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder processing applications caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. potentiometer characteristics over recommended operating condi tions, unless otherwise stated. symbol parameter test conditions limits unit min typ max end-to-end resistance tolerance 20 % v vh v h terminal voltage - v cc + v cc v v vl v l terminal voltage - v cc + v cc v r w wiper resistance i w = (v h - v l )/r total , v cc = 5v 40 100 ? i w wiper current 4.4 ma noise (note 5) ref: 1khz -120 dbv resolution 3% absolute linearity (note 1) r w(n)(actual) - r w(n)(expected) 1 mi (note 3) relative linearity (note 2) r w(n+1) - (r w(n) +mi) 0.2 mi (note 3) r total temperature coefficient (note 5) 300 ppm/c ratiometric temperature coefficient (note 5) 20 ppm/c c h /c l /c w (note 5) potentiometer capacitances see circuit #3 10/10/25 pf notes: 1. absolute linearity is utilized to determine actual wiper volt age versus expected voltage = (v w(n)(actual) - v w(n)(expected) ) = 1 mi maximum. 2. relative linearity is a measure of the error in step size bet ween taps = r w(n+1) - (r w(n) + mi) = 0.2 mi. 3. 1 mi = minimum increment = r tot /31. x9313
6 fn8177.7 october 7, 2015 submit document feedback dc electrical specifications over recommended operating condi tions, unless otherwise stated. symbol parameter test conditions/notes limits unit min typ (note 4) max i sb v cc active current cs = v il , u/d = v il or v ih and inc = 0.42/2.4v @ max t cyc 13ma standby supply current cs = v cc - 0.3v, u/d and inc = v ss or v cc - 0.3v 200 500 a i li cs , inc , u/d input leakage current v in = v ss to v cc 10 a v ih cs , inc , u/d input high current 2 v v il cs , inc , u/d input low current +0.8 v c in (note 5) cs , inc , u/d input capacitance v cc = 5v, v in = v ss , t a = +25c, f = 1mhz 10 pf endurance and data retention parameter min unit minimum endurance 100,000 data changes per bit per register data retention 100 years figure 1. test circuit #1 figure 2. test circuit #2 figure 3. circui t #3 spice macro model test point v w /r w v h /r h v l /r l v s force current vw test point v h /r h v w /r w v l /r l c h c l r w 10pf 10pf r h r l r total c w 25pf x9313
7 fn8177.7 october 7, 2015 submit document feedback power-up and power-down requirements the recommended power-up sequence is to apply v cc /v ss first, then the potentiometer vo ltages. during power-up, the data sheet parameters for the dc p do not fully apply until 1ms after v cc reaches its final value. the v cc ramp specification is always in effect. in order to prevent unwanted tap position changes, or an inadvertent s tore, bring the cs and inc high before or concurrent ly with the vcc pin on power-up. ac electrical specifications over recommended operating condit ions, unless otherwise stated. symbol parameter limits unit min typ (note 4) max t ci cs to inc setup 100 ns t id inc high to u/d change 100 ns t di u/d to inc setup 2.9 s t il inc low period 1 s t ih inc high period 1 s t ic inc inactive to cs inactive 1 s t cph cs deselect time (store) 20 ms t cph cs deselect time (no store) 100 ns t iw inc to v w change 5 s t cyc inc cycle time 2 s t r , t f (note 5) inc input rise and fall time 500 s t pu (note 5) power-up to wiper stable 10 s t r v cc (note 5) v cc power-up rate 0.2 50 v/ms t wr (note 5) store cycle 10 ms notes: 4. typical values are for t a = +25c and nominal supply voltage. 5. this parameter is not 100% tested. cs inc u/d v w t ci t il t ih t cyc t id t di t iw mi (see note) t ic t cph t f t r 10% 90% 90% note: mi in the ac timing diagram refers to the minimum increme ntal change in the v w output due to a change in the wiper position. figure 4. ac timing diagram x9313
8 fn8177.7 october 7, 2015 submit document feedback applications information electronic digitally controlled potentiometers (xdcp) provide three powerful applic ation advantages: 1. the variability and reliability of a solid-state potentiomete r. 2. the flexibility of comput er-based digital controls. 3. the retentivity of nonvolat ile memory used for the storage of multiple potentiome ter settings or data. basic configurations of electronic potentiometers basic circuits v r v w /r w v r i three-terminal potentiometer; variable voltage divider two-terminal variable resistor; variable current v h v l cascading techniques buffered refe rence voltage C + +5v r 1 +v -5v vw v ref v out op-07 v w vw/rw +v +v +v x (a) (b) v out = v w /r w noninverting amplifier + C v s v o r 2 r 1 v o = (1 + r 2 /r 1 )v s lm308a voltage regulator r 1 r 2 i adj v o (reg) = 1.25v (1 + r 2 /r 1 ) + i adj r 2 v o (reg) v in 317 offset voltage adjustment + C v s v o r 2 r 1 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 comparator with hysteresis v ul = [r 1 /(r 1 + r 2 )] v o (max) v ll = [r 1 /(r 1 + r 2 )] v o (min) + C v s v o r 2 r 1 } } lt311a +5v -5v (for additional circuits see an115)
9 fn8177.7 october 7, 2015 submit document feedback about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change october 7, 2015 fn8177.7 added revision history beginning with re v 7. added about intersil verbiage. updated ordering information on page 2. dc electrical spec table on page 6 - changed i cc for parameter v cc active current to i sb updated pod m8.118 to most curren t revision with changes as fol lows: corrected lead width dimension in side view 1 from "0.25 - 0.03 6" to "0.25 - 0.36" updated to new intersil format by adding land pattern and movin g dimensions from table onto drawing. updated pod m8.15 to most curr ent revision with changes as foll ows: changed note 1 "1982" to "1994" changed in typical recommended land pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) updated to new pod format by remo ving table and moving dimensio ns onto drawing and adding land pattern. x9313
10 fn8177.7 october 7, 2015 submit document feedback x9313 package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
11 fn8177.7 october 7, 2015 submit document feedback x9313 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or ga te burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. package width does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are s hown for reference only. 6. the lead width as measured 0.36m m (0.014 inch) or greater abo ve the seating plane, shall not exceed a maximum value of 0.61mm (0.02 4 inch). 7. controlling dimension: millimete r. converted inch dimensions a re not necessarily exact. 8. this outline conforms to je dec publication ms-012-aa issue c . side view a side view b 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)
12 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn8177.7 october 7, 2015 submit document feedback x9313 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions o f 0.010 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions e and ea are measu red with the leads constrained p erpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c

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